This invention relates to a test circuit and a test method for testing semiconductor chips which are arranged on a board and are electrically connected to each other.
Conventionally, suggestion has been made about a method (thereinafter, referred to as an internal scan) for forming an internal scan path inside a semiconductor chip to test whether or not logic circuits in the semiconductor chip normally operate. The internal scan is mainly used to test the respective semiconductor chips.
On the other hand, another suggestion has been made about a test method (thereinafter, referred to as a boundary scan) due to a boundary scan for testing whether or not the semiconductor chips are normally connected to each other on the board. The boundary scan is standardized by IEEE 1149.1. In this case, TDI, TDO, TCK, TMS and TRST terminals must be provided for the boundary scan.
Recently, it has been required to check normality of the individual chips in addition to the connection relation between the semiconductor chips which are arranged on the board and are electrically connected to each other. To comply with the requirement, it is necessary to perform the internal scan as well as the boundary scan on the condition that the semiconductor chips are arranged on the board.
A semiconductor integrated circuit in which the boundary scan and the internal scan are performed together is disclosed in Japanese Unexamined Patent Publication No. H5-142307 (reference 1), Japanese Unexamined Patent Publication No. H7-63821 (reference 2) and Japanese Unexamined Patent Publication No. H5-72273 (reference 3). The semiconductor integrated circuit disclosed in the reference 1 has logic circuits, a test circuit for performing the boundary scan test, and a specific cell which is used during the boundary scan. With this structure, the specific cell is used as a control signal supply path for the logic circuits by an instruction.
In this event, the above specific cell has a system clock terminal, and clock pulses are supplied for the logic circuits via the system clock terminal during the internal scan. However, although the boundary scan is conducted independent from the internal scan with such a structure, the system clock terminal which is used only during the internal scan is additionally necessary. Therefore, the internal scan can not be performed by the use of only the terminals standardized by the above IEEE 1149.1, namely TDI, TDO, TCK, TMS and TRST terminals. Consequently, the number of the terminals is increased in the reference 1. Further, an internal scan resistor for the internal scan and a boundary scan resistor for the boundary scan can not be operated at the same time in the reference 1. This means that the internal scan must be performed after an instruction for shifting the internal scan resistor is set and further the boundary scan must be conducted after an instruction for shifting the boundary scan resistor is set again. Therefore, a long time is necessary to perform the internal scan and the boundary scan.
On the other hand, the reference 2 discloses a test circuit in which at least a part of the boundary scan resistor is used as a parallel/serial converter or a serial/parallel converter during the internal scan and thereby, a scan data is inputted and outputted via the converter. However, the terminal which is exclusively used for the internal scan is necessary like the reference 1. Consequently, the terminal number is also inevitably increased in the reference 2.
In the above references 1 and 2, an additional circuit for the internal scan is required when the internal scan is carried out on the board.
In addition, the reference 3 discloses an integrated circuit device in which the boundary scan is performed with a sequence specified by IEEE 1149.1 and further, the internal scan is also conducted. The internal scan is realized by operating a scan path and a by-pass scan path consisting of a scan path select circuit in accordance with the sequence of the boundary scan specified by the above IEEE 1149.1.
However, such a structure is complicated and therefore, it is difficult to apply to a general circuit, since it is necessary to provide a specific circuit such as the by-pass scan path in the integrated circuit device.